We’re happy to announce the launch of Raspberry Pi Pico 2, our second-generation microcontroller board, built on RP2350: a new high-performance, secure microcontroller designed here at Raspberry Pi.
With a higher core clock speed, twice the memory, more powerful Arm cores, new security features, and upgraded interfacing capabilities, Pico 2 delivers a significant performance and feature uplift, while retaining hardware and software compatibility with earlier members of the Pico series.
So, two years ago, with the RP1 I/O controller for Raspberry Pi 5 in the bag, the Raspberry Pi chip team started work on what would become RP2350. This is a vastly more sophisticated design than RP2040, featuring:
Two 150MHz Arm Cortex-M33 cores, with floating point and DSP support
520KB of on-chip SRAM in ten concurrently accessible banks
A comprehensive security architecture, built around Arm TrustZone for Cortex-M, and including:
Signed boot support
8KB of on-chip antifuse one-time-programmable (OTP) memory
SHA-256 acceleration
A hardware true random number generator (TRNG)
An on-chip switch-mode power supply and low-quiescent-current LDO
Twelve upgraded PIO state machines
A new HSTX peripheral for high-speed data transmission
Support for external QSPI PSRAM
Apart from two Arm cores, there are also 2 RISC-V cores lurking in there!
Although we’ve been a member of RISC-V International for many years, we’ve never found an opportunity to ship a RISC-V Raspberry Pi product. But that’s changing today, thanks to a bonus feature of RP2350: a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores. Our boot ROM can even auto-detect the architecture for which a second-stage binary has been built and reboot the chip into the appropriate mode. All features of the chip, apart from a handful of security features, and the double-precision floating-point accelerator, are available in RISC-V mode.
Hazard3 was developed by Luke Wren, currently a Principal Engineer in the Raspberry Pi chip team, in his free time. As a solo project, it’s an intellectual tour de force: a highly optimised three-stage pipelined processor, implementing the RV32I instruction set, and a large collection of standard extensions targeting performance and code density. If you’d like to know more, I recommend a browse through Luke’s historical posts on Twitter/X, which cover the development process in considerable detail.
In adding Hazard3 to RP2350, we’re aiming to give software developers a chance to experiment with the RISC-V architecture in a stable, well-supported environment, and to popularize Hazard3 as a clean, open core, suitable for verbatim use in other devices, or as a basis for further development.
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